1. Field of the Invention
This invention relates to a digital signal processor (DSP) best suited for the equalization of acoustic signals, the reproduction of sound field, the addition of reverberation, etc.
2. Description of the Related Art
In a DSP used for control of sound quality through various types of filtering, including graphic equalizers, a desired sound quality is obtained by changing the coefficient data on the filters. For a DSP used to reproduce a sound field space that gives the feeling of being at a live performance in a concert hall or the like, the reproduction of sound field or the addition of reverberation is achieved, simulating its echo pattern or impulse response. To achieve this, it is necessary for the DSP to change the data (the multiplier's coefficient data or the RAM's offset address data) necessary for multiplication or for address generation for the data delay RAM, in accordance with the music software and the conditions of the listening room.
To change the above data, the circuits as shown :in FIGS. 1 and 3 are used. Each of FIGS. 1 and 3 show a portion of a conventional DSP, centering on the circuitry related to data change.
The circuit of FIG. 1 rewrites the data based on the data latch pulses used when the control device such as a microcomputer transmits the data to be changed. This circuit is composed of a pointer & data write control circuit 11, a serial input register (SIPO) 12, a decoder (DEC) 9, a write address pointer 13, pointers 14-1 and 14-2, selectors 15-1 and 15-2, a coefficient RAM 16 and an offset data RAM 10. The circuit thus constructed is supplied with a data latch pulse SA used to take in the data, command and data SB, and data shift clock SC, as shown in FIG. 2. The data latch pulse is supplied to the pointer & data write control circuit 11, the output of which is supplied to the control input terminal CK of the write address pointer 13 and the read/write signal input terminals R/W of the coefficient RAM 16 and the offset data RAM 10. The serial input register 12 receives the command and data SB at its data input terminal D and the data shift clock SC at its clock input terminal CK. The command from the output terminal O of the register 12 is supplied to the decoder 9 while the data is supplied to the write address pointer 13 and data input terminals I of the RAMs 16 10. The decoder 9 is decodes the command from the register 12, thus producing a write control signal which data is to be written into the pointer 13 and RAMs 16 and 10. On the other hand, the program sets read addresses in the pointers 14-1 and 14-2, respectively. The addresses from the pointers 13 and 14-1 are supplied to the selector 15-1, which then selects one of those addresses and supplies it to the address input terminal A of the RAM 16. The data read out of the output terminal O of the RAM 16 is supplied to a multiplier (MPY). The addresses from the pointers 13 and 14-2 are supplied to the selector 15-2, which then selects one of those addresses and supplies it to the address input terminal A of the RAM 10. The data read out of the output terminal O of the RAM 10 is supplied to an address generator circuit (AGEN) that produces addresses for an externally connected RAM.
With this configuration, to change the data, the selectors 15-1 and 15-2 select the pointer 13. The command and data SB is read into the serial input register 12 in synchronization with the shift clock pulse SC. When the data latch pulse goes to the low level, the output of the pointer & data write control circuit 11 brings the RAM 16 or 10 into the write mode and the pointer 13 is into the active state. At this time, the command from the register 12 is supplied to the decoder 9, which in turn decodes it, generates an address in the selected RAM 16 or RAM 10, and supplies the address to the input terminal A of the selected RAM 16 or RAM 10. This allows the data from the register 12 to be stored sequentially into the location with the address in the selected RAM 16 or RAM 10 specified by the pointer 13, thereby rewriting the data.
In reading data, the selectors 15-1 and 15-2 select the pointers 14-1 and 14-2, which in turn specifies an address in the RAM 16 or RAM 10. From the location with this address, the data is read and supplied to the multiplier (MPY) or the address generator circuit (AGEN).
With this arrangement, however, the data write signal is produced using the data latch pulse SA, so that it is unknown where the data write signal appears in the progress of the program. There may be a case where the data write signal appears in the course of processing or computing signals. Should this happen, it is impossible to read the data necessary for calculation or access to the data delay RAM, which results in abnormal signal processing, leading to the interruption of sound or the generation of noise.
In the circuit of FIG. 3, the instruction RAM corresponding to a single unit of signal processing is provided with an empty area that is not used for signal processing, but stores data, and the rewriting of data is done by a conditional branch process. This type of DSP is disclosed in, for example, User's Manual for .mu.PD6380, IEU-652 Chap. 4, Sec. 4. 2. 1, "Program RAM and Coefficient Data RAM Rewriting," and Chap. 4, Sec 4. 2. 2, "Coefficient Data RAM Rewriting," December, 1988. This circuit is made up of an interface circuit (I/F) 17, a program RAM (instruction RAM) 18, a program counter (PC) 19, an instruction decoder (DEC) 20, a data bus 21, a coefficient RAM 22, and a coefficient RAM pointer (CP) 23. The data from a control device 24 such as a microcomputer is supplied to the data input terminal I of the program RAM (PRAM) 18 via the interface circuit 17, while the write PC address is supplied to the program counter 19. The output of the counter 19 is supplied to the address input terminal of the PRAM 18. The output terminal O of the PRAM 18 is connected to the instruction decoder 20. The instruction read from the PRAM 18 is decoded by the decoder 20, which produces a jump address, the control signal for each circuit, and immediate data. The jump address is supplied to the program counter 19. The immediate data is supplied onto the data bus 21, to which the data input/output terminal I/O of the coefficient RAM 22 and its pointer 23 are connected. The coefficient data read from the coefficient RAM 22 is supplied to, for example, a multiplier (MPY) (not shown).
The circuit of FIG. 3 is set with sampling periods N-1, N, N+1, . . . by channel clock LRCK indicating the sampling cycle as shown in FIG. 4. During the "H" level period of this sampling cycle, the left-channel (Lch) data is input to the circuit; during the "L" level period of the sampling cycle, the right-channel (Rch) data is input to the circuit. Each sampling period contains signal processing steps ST1, ST3, ST5, . . . and rewriting steps for coefficient data or offset data ST2, ST4, ST6, . . .
Since the rewriting of data in the coefficient RAM 22 is done using a particular instruction (an immediate data load instruction), as many instructions as the data items to be rewritten are to be written into the program area in the PRAM 18 corresponding to the data rewrite execution steps. This instruction data for rewriting is written from the external control device (microcomputer) 24 into the PRAM 18 via the interface circuit 17. At the beginning of the data rewrite execution program, an instruction is placed which sets an address at which rewriting starts.
Control remains stopped at the conditional operation instruction without executing the data rewrite program until the microcomputer 24 has finished writing into the PRAM 18 as much rewrite instruction data as the amount of data to be rewritten by the conditional operation instruction (for example, a conditional jump instruction) placed at the end of the signal processing program.
When the microcomputer 24 has completed rewriting that amount of data into the PRAM 18, it sends a rewrite request flag to the DSP. After the signal processing step has be executed during the sampling period (the Nth sampling in FIG. 5) next to the sampling during which the DSP has received that rewrite flag, the data rewrite step is executed by means of the conditional operation step. After all data has been rewritten, the rewrite request flag is cleared, and during the next sampling period and later, only signal processing steps will be executed as described earlier.
The number of program steps the DSP can execute during a single sampling period is finite. Using all such a finite number of sampling steps for signal processing allows the DSP to provide its full power. In the method shown in FIGS. 3 to 5, however, instead of using all program steps, executable during one sampling period, for signal processing, those steps are divided into signal processing steps and data (coefficient data or offset address data) rewrite program steps. The data is rewritten by means of a conditional operation instruction. Thus, the greater the amount of data to be rewritten, the more the DSP's signal processing capability reduces. This imposes on the control device 24 the serious burden of transmitting an instruction each time a parameter is rewritten.
In addition, the aforementioned two methods have disadvantages in that, particularly in the case of the gain control coefficients to be rewritten, the waveform of the acoustic signal may be discontinuous with the timing that the coefficient data changes, creating noises.